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DRAM
FEATURES
y y y y y y y y y
M11B11664A 64 K x 16 DRAM
EDO PAGE MODE
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ 44 / 40-pin 400mil TSOP (TypeII)
X16 organization EDO (Extended Data-Output) access mode 2 CAS Byte/Word Read/Write operation Single 5V ( 10%) power supply TTL-compatible inputs and outputs 256-cycle refresh in 4ms Refresh modes : RAS only, CAS BEFORE RAS (CBR) and HIDDEN JEDEC standard pinout Key AC Parameter tRAC -25 -30 -35 -40 25 30 35 40 tCAC 8 9 10 11 tRC 43 55 65 75 tPC 10 12 14 16
PRODUCT NO. M11B11664A-25J M11B11664A-30J M11B11664A-35J M11B11664A-40J M11B11664A-25T M11B11664A-30T M11B11664A-35T M11B11664A-40T
PACKING TYPE
SOJ
TSOPII
GENERAL DESCRIPTION
The M11B11664A is a randomly accessed solid state memory, organized as 65,536 x 16 bits device. It offers Extended Data-Output , 5V( 10%) single power supply. Access time (-25,-30,-35,-40) and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities. Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
VC C I/O0 I/O1 I/O2 I/O3 VC C I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VC C
TSOP (TypeII) Top View
VS S I/O1 5 I/O1 4 I/O1 3 I/O1 2 VS S I/O1 1 I/O1 0 I/O9 I/O8 NC CA SL C ASH OE NC A7 A6 A5 A4 VS S
VC C I/O 0 I/O 1 I/O 2 I/O 3 VC C I/O 4 I/O 5 I/O 6 I/O 7 NC NC WE RA S NC A0 A1 A2 A3 VC C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
V SS I/O 15 I/O 14 I/O 13 I/O 12 V SS I/O 11 I/O 10 I/O 9 I/O 8 NC C AS L C AS H OE NC A7 A6 A5 A4 V SS
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 1/15
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FUNCTIONAL BLOCK DIAGRAM
WE RAS CASL CASH CONTROL LOGIC DATA-IN BUFFER
M11B11664A
16
IO0 : IO15
CLOCK GENERATOR
DATA-OUT BUFFER 8 COLUMN DECODER 256 16 OE 16
8 A0 A1 A2 A3 A4 A5 A6 A7 8
COLUMN ADDRESS BUFFER
REFRESH CONTROLER
SENSE AMPLIFIERS I/O GATING 8 256 x 16
REFRESH COUNTER 89 ROW. ADDRESS BUFFERS(8) 8 ROW DECODER
256
256 x 256 x 16 MEMORY ARRAY
VCC VBB GENERATOR VSS
PIN DESCRIPTIONS
PIN NO. 16~19,22~25 14 28 29 13 27 2~5,7~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 PIN NAME A0~A7
RAS CASH CASL WE OE
TYPE Input Input Input Input Input Input Input / Output Supply Ground -
DESCRIPTION Address Input Row Address : A0~A7 Column Address : A0~A7 Row Address Strobe Column Address Strobe / Upper Byte Control Column Address Strobe / Lower Byte Control Write Enable Output Enable Data Input / Output Power, 5V Ground No Connect
I/O0 ~ I/O15 VCC VSS NC
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 2/15
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss ... ......-1V to +7V Operating Temperature, TA (ambient) ....0 C to +70 C Storage Temperature (plastic) ..........-55 C to +150 C Power Dissipation .......................................1.0W Short Circuit Output Current ........................50mA
M11B11664A
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0 C TA 70 C ; VCC = 5V 10% unless otherwise noted)
PARAMETER Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note : 1.All Voltages referenced to VSS 0V VIH 7V 0V VOUT 7V Output(s) disable IOH = -5 mA IOL = 4.2 mA CONDITIONS SYMBOL VCC VSS VIH VIL ILI ILO VOH VOL MIN 4.5 0 2.4 -1.0 -10 -10 2.4 MAX 5.5 0 VCC +1 0.8 10 10 0.4 UNITS NOTES V V V V A A V V 1 1 1
PARAMETER Operating Current Standby Current
CONDITIONS
RAS , CAS cycling , tRC =min
SYMBOL ICC1 ICC2
MAX -25 -30 -35 -40 170 150 130 120 4 2 4 2 4 2 4 2
UNITS NOTES
mA mA mA mA mA mA mA
1,2
TTL interface , RAS , CAS = VIH , DOUT =High-Z CMOS interface, RAS , CAS VCC-0.2V
RAS only refresh Current
tRC = min tPC = min
RAS =VIH, CAS = VIL
ICC3 ICC4 ICC5 ICC6
170 150 130 120 170 150 130 120 5 5 5 5
2 1,3 1
EDO Page Mode Current Standby Current
CAS Before RAS Refresh Current
tRC = min
170 150 130 120
Note : 1. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS =VIL . 3. Address can be changed once or less while CAS =VIH .
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 3/15
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CAPACITANCE (Ta = 25 C , VCC = 5V 10%)
PARAMETER Input Capacitance (address) Input Capacitance ( RAS , CASH , CASL , WE , OE ) Output capacitance (I/O0~I/O15) SYMBOL CI1 CI2 CI / O TYP MAX 5 7 10
M11B11664A
UNIT pF pF pF
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 C , VCC =5V 10%, VSS = 0V) (note 14)
Test Conditions Input timing reference levels : 0V, 3V Output reference level : VOL= 0.8V, VOH=2.0V Output Load : 2TTL gate + CL (50pF) Assumed tT = 2ns PARAMETER Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time EDO-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge
RAS Pulse Width RAS Pulse Width (EDO Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time
SYMBOL tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS tRASC tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL
-25 MIN 43 65 10 32 25 8 8 12 14 25 10,000 30 MAX MIN 55 85 12 37
-30 MAX MIN 65 95 14 42 30 9 9 15 17 10,000 35
-35 MAX MIN 75 105 16 47 35 10 10 18 20 10,000 40
-40 MAX
UNIT Notes ns ns ns ns 22 22 4 5,20 13,20 20
40 11 11 20 22 10,000
ns ns ns ns ns ns ns ns ns
25 100,000 30 100,000 35 100,000 40 100,000 8 15 4 21 4 10 5 0 5 8 0 5 22 12 13 17 10,000 9 20 5 26 4 10 5 0 5 8 0 5 26 15 15 21 10,000 10 25 5 30 5 10 5 0 5 8 0 5 30 18 17 25 10,000 11 30 6 35 5 10 5 0 5 8 0 5 34 20 20 29 10,000
25
ns ns ns ns ns ns ns ns ns ns ns ns
24 19 6,23 7,18 19
Row Address Setup Time Row Address Hold Time
RAS to Column Address Delay Time
8 18 18
Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 4/15
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(Continued)
-25 PARAMETER Read Command Setup Time Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
M11B11664A
-30
-35
-40
UNIT
Notes
SYMBOL tRCS tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tOES tOEHC tOEP tORD tCLCH tCOH tWHZ tRSR tRHR
MIN MAX MIN MAX MIN MAX MIN MAX
0 0 0 3 3 15 6 0 5 22 5 7 5 0 5 22 34 21 17 1.5 10 5 7 4 4 2 2 0 4 3 3 5 5 7 50 4
0 0 0 3 3 15 8 0 5 26 5 8 6 0 5 26 46 31 25 1.5 10 10 10 4 4 2 2 0 5 3 3 5 5 7 50 4
0 0 0 3 3 15 8 0 5 30 5 9 7 0 5 30 51 34 26 2.5 10 10 10 4 4 2 2 0 5 3 3 5 5 7 50 4
0 0 0 3 3 15 8 0 5 34 5 10 8 0 5 34 56 36 27 2.5 10 10 10 5 5 2 2 0 6 3 3 5 5 7 50 4
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns
15,18 9,15,19 9 20 10,17,20 17,26 11,15,18 15,25 15 15 15 15,19 12,20 12,20
Output Buffer Turn-off Delay From CAS or RAS Output Buffer Turn-off to OE Write Command Setup Time Write Command Hold Time Write Command Hold Time(Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
11 11 11,18 2,3
Column Address to WE Delay Time
CAS to WE Delay Time
Transition Time (rise or fall) Refresh Period (256 cycles)
RAS to CAS Precharge Time CAS Setup Time(CBR REFRESH) CAS Hold Time(CBR REFRESH) OE Hold Time From WE During Read-ModeWrite Cycle OE Low to CAS High Setup Time OE High Hold Time From CAS High OE Precharge Time OE Setup Prior to RAS During Hidden Refresh Cycle
1,18 1,19 16
Last CAS Going Low to First CAS Returning High Data Output Hold After CAS Returning Low Output Disable Delay From WE Read Setup Time Reference to RAS in CBR Read Hold Time Reference to RAS in CBR
21
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 5/15
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Notes : 1. 2. Enables on-chip refresh and address counters. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Assume that tRCD tRCD (max) If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and
RAS must be pulsed high.
M11B11664A
back to VIH ) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE -controlled) cycle. 12. Those parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY- WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFYWRITE operation is not possible. 14. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. WRITE command is defined as WE going low. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. Referenced to the earlier CAS falling edge.
3.
4.
5. 6.
7.
8.
9. 10. 11.
Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF1(max) defines the time at which the output achieves the open circuit condition ; it is not a reference to VOH or VOL. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFYWRITE cycle only. If tWCS tWCS(min) , the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min) , tAWD tAWD(min) and tCWD tCWD(min) , the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
15. 16.
17. 18.
19. Referenced to the latter CAS rising edge. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO0~7 by CASL and IO8~15 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle's last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. Each CAS must meet minimum pulse width. 25. Referenced to the latter CAS failing edge. 26. All IOs controlled by OE , regardless CASL and
CASH .
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 6/15
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TRUTH TABLE
ADDRESSES
RAS CASL CASH
M11B11664A
FUNCTION Standby Read : Word Read : Lower Byte Read : Upper Byte Write : Word (Early Write) Write : Lower Byte (Early)
WE X H H H L L
OE
DQS High-Z Data-Out Lower Byte, Data-Out Upper Byte, Data-Out Data-In Lower Byte, Data-In , Upper Byte, High-Z Lower Byte, High-Z , Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-Out
NOTES
ROW X ROW ROW ROW ROW ROW
COL X COL COL COL COL COL
H L L L L L
HAEX L L H L L
HAEX L H L L H
X L L L X X
Write : Upper Byte (Early) Read-Write 1st Cycle EDO-Page-Mode 2nd Cycle Read Any Cycle EDO-Page-Mode 1st Cycle Write 2nd Cycle EDO-Page-Mode 1st Cycle Read-Write 2nd Cycle Hidden Refresh
RAS -Only Refresh
L L L L L L L L L LAEHAEL L HAEL
H L HAEL HAEL LAEH HAEL HAEL HAEL HAEL L H L
L L HAEL HAEL LAEH HAEL HAEL HAEL HAEL L H L
L
X
ROW ROW ROW
COL COL COL COL
HAEL LAEH H H H L L L L L X X
1, 2 2 2 2 1 1 1, 2 1, 2 2
ROW
COL COL
Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out High-Z
HAEL LAEH HAEL LAEH H X H L X X
ROW
COL COL
ROW ROW X
COL
CBR Refresh
X
High-Z
3
*Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active). 2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active). 3. Only one CAS must be active ( CASL or CASH ).
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 7/15
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READ CYCLE
tRC tR AS
RA S VIH VIL
M11B11664A
tRP tCSH tRS H tCAS, tCLCH
tRRH
tCRP
CA SL ,C AS H VIH VIL
tRCD
tAR t R AD tASR
AD DR VIH VIL ROW
tRAH
tAS C
tRAL tCAH
C OLUMN R OW
tRCS
WE VIH VIL
t RC H
tAA tRAC t C AC tCLZ
I/ O VO H VO L OPE N
NO TE1
tOFF 1
VAL ID DA TA
OP EN
tO AC
OE VIH VIL
tO FF 2
EARLY WRITE CYCLE
tR C tRAS
RAS V IH V IL
tRP
tC SH tRS H tCRP
CA SL ,C AS H VIH VIL
t RC D
tC AS , t C L C H
tAR t ASR
ADDR VIH VIL ROW
t R AD t R AH
tASC
COLUMN
tRAL tCAH
ROW
tWCS
tCWL tRWL tWCR tWCH tWP
WE
VIH VIL
tDS
I/O V IH V IL V IH V IL
tDHR tDH
VA LI D DAT A
OE
DON'T CARE UNDEFINED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 8/15
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READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRWC t R AS
RAS VIH VIL
M11B11664A
t RP
tCRP
CASL ,C AS H VIH VIL
tRC D
tCSH tRS H t C AS , t C L C H
tASR
AD DR V IH V IL ROW
tAR tRAD tRAH
tASC
COLUMN
t R AL t C AH
ROW
tRCS
t RWD tCWD tAWD
tCWL tRWL tWP
WE
V IH V IL
tAA tRAC t C AC tCLZ
I/ O VI/OH VI/OL OPE N VAL I D DOUT
tDS
tDH
VA LID DIN
t O AC
OE VIH VIL
tOFF 2
tOEH
EDO-PAGE-MODE READ CYCLE
t R AS C
RA S VIH VIL
tRP
tCRP
CA SL ,C ASH V IH V IL
tCSH t RC D
tP C (NOTE2) tCAS,tCLCH tCP t C AS , t C L CH tCP
tRS H tCAS,tCLCH
tCP
tAR t R AD t AS R t R A H
AD DR VIH VIL ROW
t R AL t AS C tCAH t AS C tCAH t AS C tCAH
ROW
COLUMN
COLUMN
COLUMN
tRCS
WE VIH VIL
tRC H
tRRH
tAA tRAC t C AC tCLZ
I/ O VOH VOL O PE N
tAA tACP t C AC tCOH
VALID DATA
V AL I D D ATA
tAA tACP tCAC tCLZ tOEHC tO AC t OF F2 tO ES t O EP
VAL ID DATA N O TE 1
tOF F1
OPE N
tO AC tO ES
OE VIH VIL
tOFF2
DON'T CARE
UNDEFINED
*NOTE : 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of
CAS . Both measurements must meet the tPC specification.
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 9/15
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EDO-PAGE-MODE EARLY-WRITE CYCLE
t R AS C
RAS VIH VIL
M11B11664A
tRP
tCSH tCRP
CA SL,C ASH VIH VIL
tRC D
tC A S , t C L CH
tPC (NOTE1) tCAS,t CLCH tCP
tCP
tRS H t C AS , t C L C H
tCP
tAR t R AD tASR
AD DR VIH VIL
tRAH
t AS C
tCAH
t A S C t C AH
COLUMN
t AS C
t R AL tCAH
ROW
ROW
COLUMN
COL U MN
tCWL tWCS tWCH tWP tWCS
tCWL tWCH tWP
tWCS
tCWL tWCH tWP
WE
VIH VIL
tDS
I/ O VIH VIL
t WCR tDH R tDH
tRWL tDS tDH tDS tDH
V AL I D D AT A
VALI D DATA
V AL I D D AT A
OE
VIH VIL
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRASC
RAS VIH VIL
tRP
t CS H tCRP
CASL ,CAS H VIH VIL
t RC D
t CA S , t C LC H
tCP
tPCM tCAS,t CLCH
tRSH t CP tCAS, t CLCH tCP
tAR t RA D tASR
ADDR VIH VIL
tRAH
tASC
t CA H
t AS C
t C AH
tASC
tRAL tCAH
ROW
ROW
C OL UM N
C OL UM N
COLUM N
tRWD tRCS tCWL tWP tCWL tWP tAWD t CWD t A WD tCWD
tRWL tCWL tWP
t A WD tCWD
WE VIH VIL
tAA t R AC t C AC t CL Z
I/ O VI /O H VI /O L
V A L I D VA L I D DOUT DI N
tAA t DH tDS tACP t C AC tCLZ
VALI D VAL ID DOUT DIN
tAA tDH tDS t AC P t C AC tCLZ
VA L I D DOUT VA L I D DIN
tDH tDS
tOF F2 tO AC
OE VIH VIL
tOF F2 t O AC tO AC
tOFF 2 tOEH
DON'T CARE
UNDEFINED
Note : 1. tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification.
Elite Memory Technology Inc
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EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
tRAS C
RA S VIH VIL
M11B11664A
tRP
tCSH tCRP
CAS VIH VIL
t RC D
tPC tCAS
tCP tCP tCAS tCP
tRSH tCAS
tCP
tAR tRAD tASR tRAH
AD DR VIH VIL R OW
tRAL tCAH tASC tCAH tAS C tCAH
ROW
t ASC
CO LU M N(A )
COLU MN(B)
COLUMN( N)
tRCS
WE VIH VIL
tRCH
t WCS
tWCH
tA A t R AC tCAC tACP
tAA tW HZ tCAC tCO H
VA L ID DAT A( A )
VA L I D DATA(B )
tDS
tDH
I/O
VI/OH VI/OL
OPE N
VALI D DATA IN
tO AC
OE VIH VIL
RAS ONLY REFRESH CYCLE (ADDR = A0~A7 ; OE , WE = DON'T CARE)
tRC tRAS
RA S VIH VIL
tRP
tC RP
CA SL ,C A SH VIH VIL
tRP C
tAS R
AD DR VIH VIL R OW
t RAH
ROW
I/O
VOH VOL
OPE N
DON'T CARE
UNDEFINED
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CBR REFRESH CYCLE (A0~A7 ; OE = DON'T CARE)
tRP
RAS VIH VIL
M11B11664A
tRAS
tRP
t R AS
tR PC tCP
CA SL , C AS H VIH VIL
tCS R
tCHR
tR PC
tCSR
tCHR
I/O
VOH VOL
OPE N
t RC H
WE V IH V IL
t R S R t RH R
( NOT E1 )
tR SR
tRHR
HIDDEN REFRESH CYCLE WE = HIGH ; OE = LOW
( RE AD )
( R EF RE S H )
t RAS
RAS VIH VIL
tRP
t RAS
tC RP
CA SL ,CAS H VIH VIL
t RC D
tRSH
tCHR
tAR tRAD tASR tRAH
ROW
t ASC
tRAL tCAH
ADDR
VIH VIL
CO LU MN
tAA t RAC t CAC tCLZ
I/O VO H VO L OP EN VAL ID DAT A
NOTE2
tO FF 1
OPE N
tO AC tORD
OE VIH VIL
tO FF
2
DON'T CARE
UNDE FINED
Note : 1. tRSR and tRHR are for system design reference only. The WE signal is actually a "don't care" at RAS time during a CBR REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CBR REFRESH. 2. tOFF1 is reference from the rising edge of RAS or CAS , whichever occurs last.
Elite Memory Technology Inc
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PACKING 40-LEAD SECTIONI
' E
M11B11664A
DIMENSIONS SOJ(400mil)
0$;
( (
E
'(7$,/ $
$ $ H '(7$,/ $ 0,1 F $ 5
; (
SECTIONII
Symbol A A1 A2 b b2 c e D
Dimension in mm Min Norm Max 3.250 3.510 3.760 2.080 2.790 REF 0.380 0.460 0.560 0.635 REF 0.180 0.250 0.360 1.270 BSC 25.91 26.040 26.290
Dimension in inch Symbol Dimension in mm Min Norm Max Min Norm Max 0.128 0.138 0.148 E 10.920 11.176 11.430 0.082 E1 10.030 10.160 10.290 0.110 REF E2 9.40 BSC 0.015 0.018 0.022 R1 0.760 0.890 1.020 0.025 REF b2 0.635 REF 0.007 0.010 0.014 1 1.02 0.050 BSC 1.025 1.035 e y1 1.270 BSC 0.381
Dimension in inch Min Norm Max 0.430 0.440 0.450 0.395 0.400 0.405 0.370 BSC 0.030 0.035 0.040 0.025 REF

0.050 BSC 0.015
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Publication Date : Dec. 2000 Revision : 1.3 13/15
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PACKING 40 / 44-LEAD DIMENSIONS TSOP(II) DRAM(400mil)
M11B11664A
Symbol A A1 A2 b b1 c c1 D ZD E E1 L L1 e
Dimension in mm Min 0.05 0.95 0.30 0.30 0.12 0.10 18.28 11.56 10.03 0.40 18.41 0.805 REF 11.76 10.16 0.59 0.80 REF 0.80 BSC O ~ 7 REF 11.96 10.29 0.69 0.35 1.00 Norm Max 1.20 0.15 1.05 0.45 0.40 0.21 0.16 18.54
Dimension in inch Min 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.455 0.395 0.016 0.725 0.0317 REF 0.463 0.400 0.023 0.031 REF 0.0315 BSC O ~ 7 REF 0.471 0.4 0.027 0.014 0.039 Norm Max 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730
Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 14/15
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Elite Memory Technology Inc
Publication Date : Dec. 2000 Revision : 1.3 15/15

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